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November 2006 rev 1.4 LCD Panel EMI Reduction IC
Features
* * * * * * * * * * * *
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P2042A
interference (EMI) at the clock source, allowing system wide reduction of EMI of down stream clock and data dependent signals. The P2042A allows significant system cost savings by reducing the number of circuit board layers ferrite beads, regulations. The P2042A uses the most efficient and optimized modulation profile approved by the FCC and is implemented in a proprietary all digital method. The P2042A modulates the output of a single PLL in order to "spread" the bandwidth of a synthesized clock, and more importantly, decreases the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most frequency generators. Lowering EMI by increasing a signal's bandwidth is called `spread spectrum clock generation'. shielding and other passive components that are traditionally required to pass EMI
FCC approved method of EMI attenuation. Provides up to 15dB of EMI suppression. Generates a low EMI spread spectrum clock of the input frequency. Input frequency range: 30MHz to 110MHz. Optimized for 32.5MHz, 54MHz, 65MHz and 108MHz pixel clock frequencies. Internal loop filter minimizes external components and board space. Eight selectable high spread ranges up to 1.9%. SSON# control pin for spread spectrum enable and disable options. Low cycle-to-cycle jitter. 3.3V 0.3V operating range. Low power CMOS design. Supports most mobile graphic accelerator and LCD timing controller specifications. Available in 8-pin SOIC and TSSOP Packages.
Product Description
The P2042A is a versatile spread spectrum frequency modulator designed specifically for digital flat panel applications. The P2042A reduces electromagnetic
Applications
The P2042A is targeted towards digital flat panel applications for notebook PCs, palm-size PCs, office automation equipments and LCD monitors.
Block Diagram
VDD SR0 CP1 CP0 SSON#
Modulation CLKIN Frequency Divider Feedback Divider
PLL
Phase Detector
Loop Filter
VCO
Output Divider ModOUT
VSS
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200, Campbell, CA 95008 * Tel: 408-879-9077 * Fax: 408-879-9018 www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
November 2006 rev 1.4
Pin Configuration
CLKIN 1 CP0 2
8
P2042A
VDD
7 SR0
P2042A
CP1 3 VSS 4
6 5
ModOUT SSON#
Pin Description Pin#
1 2 3 4 5 6 7 8
Pin Name
CLKIN CP0 CP1 VSS SSON# ModOUT SR0 VDD
Type
I I I P I O I P
Description
External reference frequency input. Connect to externally generated reference signal. Digital logic input used to select charge pump current. This pin has an internal pull-up resistor. Refer Modulation Selection Table. Digital logic input used to select charge pump current. This pin has an internal pull-up resistor. Refer Modulation Selection Table. Ground to entire chip. Connect to system ground. Digital logic input used to enable Spread Spectrum function (Active LOW). Spread Spectrum function enabled when LOW, disabled when HIGH. This pin has an internal pull-low resistor. Spread spectrum clock output. Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor. Power supply for the entire chip
Modulation Selection CP0
0 0 0 0 1 1 1 1
CP1
0 0 1 1 0 0 1 1
SR0
0 1 0 1 0 1 0 1
Spreading Range (%) 32.5MHz
0.56 1.94 1.36 1.92 1.24 1.91 0.91 1.47
54MHz
1.05 1.68 1.05 1.68 0.81 1.29 0.45 0.71
65MHz
1.00 1.56 1.00 1.56 0.66 1.02 0.34 0.54
81MHz
0.98 1.48 0.92 1.48 0.40 0.74 0.05 0.36
108MHz
0.80 1.22 0.67 1.06 0.27 0.43 0.15 0.21
Modulation Rate (KHz)
(FIN /40) * 62.49 KHz
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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Spread Spectrum Selection
P2042A
The Modulation Selection Table defines the possible spread spectrum options. The optimal setting should minimize system EMI to the fullest without affecting system performance. The spreading is described as a percentage deviation of the center frequency. (Note: The center frequency is the frequency of the external reference input on CLKIN, pin1). For example, P2042A is designed for high-resolution, flat panel applications and is able to support an XGA (1024 x 768) flat panel operating at 65MHz (FIN) clock speed. A spreading selection of CP0=0, CP1=1 and SR0=0 provides a percentage deviation of 1.00% from FIN. This results in the frequency on ModOUT being swept from 65.65 to 64.35MHz at a modulation rate of 101.54KHz. Refer Modulation Selection Table. The example in the following illustration is a common EMI reduction method for a notebook LCD panel and has already been implemented by most of the leading OEM and mobile graphic accelerator manufacturers.
Application Schematic for Mobile LCD Graphics Controllers
+3.3V
65MHz from graphics accelerator
1 CLKIN 2 CP0 3 CP1 4 VSS VDD SR0 8 7 0.1F
ModOUT 6 SSON# 5
Modulated 65MHz signal with 1.00% deviation and modulation rate of 101.54KHz. This signal is connected back to the spread spectrum input pin (SSIN) of the graphics accelerator.
P2042A
Digital control for the SS enable or disable
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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November 2006 rev 1.4
Absolute Maximum Ratings Symbol
VDD, VIN TSTG TA Ts TJ TDV Storage temperature Operating temperature Max. Soldering Temperature (10 sec) Junction Temperature Static Discharge Voltage (As per JEDEC STD22- A114-B)
P2042A
Parameter
Voltage on any pin with respect to Ground
Rating
-0.5 to +4.6 -65 to +125 -40 to +85 260 150 2
Unit
V C C C C KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect device reliability.
DC Electrical Characteristics Symbol
VIL VIH IIL IIH VOL VOH IDD ICC VDD tON ZOUT Input low voltage Input high voltage Input low current (pull-up resistor on inputs CP0, CP1 and SR0) Input high current (pull-down resistor on input SSON#) Output low voltage (VDD = 3.3 V, IOL = 20 mA) Output high voltage (VDD = 3.3 V, IOL = 20 mA) Static supply current standby mode Dynamic supply current (3.3V and 10pF loading) Operating voltage Power-up time (first locked cycle after power up) Clock output impedance
Parameter
Min
VSS - 0.3 2.0 - - - 2.5 - 9 3.0 - -
Typ
- - - - - - 0.6 16 3.3 0.18 50
Max
0.8 VDD + 0.3 -35 35 0.4 - - 22 3.6 - -
Unit
V V A A V V mA mA V mS
AC Electrical Characteristics Symbol
fIN fOUT tLH* tHL* tJC tD Input frequency Output frequency Output rise time (measured at 0.8V to 2.0V) Output fall time (measured at 2.0V to 0.8V) Jitter (cycle to cycle) Output duty cycle
Parameter
Min
30 30 0.7 0.6 45
Typ
65 65 0.9 0.8 50
Max
110 110 1.1 1.0 360 55
Unit
MHz MHz nS nS pS %
*tLH and tHL are measured into a capacitive load of 15pF
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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November 2006 rev 1.4
Package Information 8-lead SOIC Package
P2042A
E
H
D
A2
A
e B A 1
C L
D
Dimensions
Symbol Min
A1 A A2 B C D E e H L
Inches Max
0.010 0.069 0.059 0.020 0.010 0.004 0.053 0.049 0.012 0.007
Millimeters Min Max
0.10 1.35 1.25 0.31 0.18 4.90 BSC 3.91 BSC 1.27 BSC 6.00 BSC 0.41 0 1.27 8 0.25 1.75 1.50 0.51 0.25
0.193 BSC 0.154 BSC 0.050 BSC 0.236 BSC 0.016 0 0.050 8
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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November 2006 rev 1.4
8-lead TSSOP
P2042A
H
E D A2 A e B A1 L C
Dimensions Symbol Min
A A1 A2 B c D E e H L 0.020 0 0.002 0.033 0.008 0.004 0.114 0.169 0.026 BSC 0.252 BSC 0.028 8 0.50 0
Inches Max
0.043 0.006 0.037 0.012 0.008 0.122 0.177 0.05 0.85 0.19 0.09 2.90 4.30
Millimeters Min Max
1.10 0.15 0.95 0.30 0.20 3.10 4.50 0.65 BSC 6.40 BSC 0.70 8
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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November 2006 rev 1.4
Ordering Information Part Number
P2042AF-08ST P2042AF-08SR P2042AF-08TT P2042AF-08TR P2042AG-08ST P2042AG-08SR P2042AG-08TT P2042AG-08TR I2042AF-08ST I2042AF-08SR I2042AF-08TT I2042AF-08TR I2042AG-08ST I2042AG-08SR I2042AG-08TT I2042AG-08TR
P2042A
Marking
P2042AF P2042AF P2042AF P2042AF P2042AG P2042AG P2042AG P2042AG I2042AF I2042AF I2042AF I2042AF I2042AG I2042AG I2042AG I2042AG
Package Type
8-Pin SOIC, TUBE, Pb Free 8-Pin SOIC, TAPE & REEL, Pb Free 8-Pin TSSOP, TUBE, Pb Free 8-Pin TSSOP, TAPE & REEL, Pb Free 8-Pin SOIC, TUBE, Green 8-Pin SOIC, TAPE & REEL, Green 8-Pin TSSOP, TUBE, Green 8-Pin TSSOP, TAPE & REEL, Green 8-Pin SOIC, TUBE, Pb Free 8-Pin SOIC, TAPE & REEL, Pb Free 8-Pin TSSOP, TUBE, Pb Free 8-Pin TSSOP, TAPE & REEL, Pb Free 8-Pin SOIC, TUBE, Green 8-Pin SOIC, TAPE & REEL, Green 8-Pin TSSOP, TUBE, Green 8-Pin TSSOP, TAPE & REEL, Green
Temperature
Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Industrial Industrial Industrial Industrial Industrial Industrial Industrial Industrial
Device Ordering Information
P 2042 A
F-
8
ST
SR - SOIC, T/R TT - TSSOP, TUBE TR - TSSOP, T/R ST - SOIC, TUBE Pin Count F = LEAD FREE AND RoHS COMPLIANT PART G = GREEN PACKAGE, LEAD FREE, and RoHS Deviation (%) and Spread option Identifier DEVICE NUMBER P = Commercial Temperature Range (0C to 70C) I = Industrial Temperature Range (-40C to 85C)
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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November 2006 rev 1.4
Licensed under U.S Patent Nos 5,488,627 and 5,631,921
P2042A
PulseCore Semiconductor Corporation 1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018 www.pulsecoresemi.com
Copyright (c) PulseCore Semiconductor All Rights Reserved Preliminary Information Part Number: P2042A Document Version: v1.4
Note: This product utilizes US Patent # 6,646,463 Impedance Emulator Patent issued to PulseCore Semiconductor, dated 11-11-2003
(c) Copyright 2006 PulseCore Semiconductor Corporation. All rights reserved. Our logo and name are trademarks or registered trademarks of PulseCore Semiconductor. All other brand and product names may be the trademarks of their respective companies. PulseCore reserves the right to make changes to this document and its products at any time without notice. PulseCore assumes no responsibility for any errors that may appear in this document. The data contained herein represents PulseCore's best data and/or estimates at the time of issuance. PulseCore reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. PulseCore does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of PulseCore products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in PulseCore's Terms and Conditions of Sale (which are available from PulseCore). All sales of PulseCore products are made exclusively according to PulseCore's Terms and Conditions of Sale. The purchase of products from PulseCore does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of PulseCore or third parties. PulseCore does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of PulseCore products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify PulseCore against all claims arising from such use.
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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